High-pixel high-definition Pixels Per Inch (PPI) products have become the mainstream for display currently in order to adapt to a higher integration level. Currently, a six-mask solution has been proposed in order to achieve the purpose of increasing throughput during the process of manufacturing thin film transistors. The core technology characteristic of Advanced Super Dimension Switch (ADS) is described as: a multi-dimensional electric field is formed from an electric field generated by an edge of a slot electrode and an electric field generated between a slot electrode layer and a plate-shaped electrode layer in a same plane, such that all oriented liquid crystal molecules between and right above slot electrodes in a liquid crystal cell are rotatable, thereby improving liquid crystal working efficiency and increasing light transmission. Advanced Super Dimension Switch can improve the image quality of TFT-LCD products, and have advantages such as high resolution, high transmittance, low power consumption, wide visual angle, high aperture ratio, low chromatic aberration, push Mura free, etc.
In an ADS mode, i.e., Fringe Field Switching (FFS) mode, an edge electric field is generated through the electrodes between pixels in a same plane such that all oriented liquid crystal molecules between and right above electrodes can be switched by rotation in a direction parallel to the plane of the substrate, thereby improving the light transmittance of the liquid crystal layer. The primary creative scheme in the 6-mask thin film transistor manufacturing process in the ADS liquid crystal display technology is that a gate insulating layer and an active layer are formed in one patterning process. For example, “a pattern comprising an active layer and a gate electrode insulating layer is formed by a third patterning process” as mentioned in the publication text of PCT patent application WO 2013143294 A1.
However, there are problems in the implementation process. As shown in FIG. 1, a gate electrode 2, a gate electrode insulating layer 3, an active layer 4, and a source-drain electrode layer 5 are formed on a substrate 1. In the wet etching step of the source-drain electrode layer 5 by a semi-transparent mask technology, since the metal material of the source-drain electrode layer 5 is indented by about 1-2 μm as compared with the photoresist, and the subsequent dry etching on the active layer 4 tends to etch in a vertical direction, the active layer 4 is almost not indented as compared with the source electrode to be formed and the upper photoresist layer covering the drain electrode. Because wet etching has the characteristic of isotropy, a width of horizontal etching is close to a depth of vertical etching. Thus, there will be a certain difference (discrepancy) between the pattern of the upper photoresist and the pattern etched on a lower material. Referring to FIG. 1, the pattern in the lower layer is the source electrode and drain electrode formed by performing wet etching on the source-drain electrode layer 5, the pattern of the upper photoresist is substantially consistent with the active layer 4, the source-drain electrode layer 5 is etched horizontally to certain extent to result in indent. Part of the active layer 4 will be etched off in a subsequent photoresist ashing, the second etching process of the source-drain electrode layer 5 and the etching process of the doped semiconductor layer on the active layer 4, thereby inevitably producing an active layer tail (a-Si tail), as shown in the area a in FIG. 1. In the trend of wiring refinement, the active layer tail will exert big load on the thin film transistor and will even affect the performance of the thin film transistor.